Aehr test systems is a worldwide provider of test systems for burnin test equipment and logic, optical and memory integrated circuits worldwide. It is a key enabler for achieving costeffective implementation of systeminpackage solutions, said gans ganesan, packaging technology manager for motorolas networking and computing systems group. The sti3000 is a waferlevel mems and mixed signal asic probe test system that combines several functional sti test equipment blocks for testing gyros, accelerometers, pressure sensors, microphones, resonators, and mixed signal asics. While our motivation is to achieve improvements over burnin of packaged parts, waferlevel burnin will actually allow us to create a manufacturing process thats much. Burnin is a temperaturebias reliability stress test used in detecting and screening out potential early life failures. It is a key enabler for achieving costeffective implementation of systeminpackage solutions, said gans ganesan, packaging technology manager. Passmark burnintest software pc reliability and load testing. Nov 15, 2018 the thin mean of wafer 80 is typically maintained at a level close to 100 c. Burnin is a temperaturebias reliability stress test used in detecting and. Waferlevel test and burnin, and semiconductor process. As of january 2019, astronics test systems has transferred ownership of the astronics systemlevel test product lines to advantest. Wafer level testing refers to a critical process of subjecting integrated circuits and semiconductor devices to electrical testing while they are still in wafer form. Electroglas provides advanced wafer probers, device handlers, test floor management software and services with modern tools for semiconductor industry.
Our technology enables customers to utilize sub30v power and device control to actively test and burnin a v device at waferlevel burnin where thousands of devices are tested in parallel. Aehr test systems to introduce next generation foxxp test. Sti3000 wafer probe test system solidus technologies. Waferlevel burnin microchips triple test flow is currently the most robust testing procedure for serial eeprom devices in. Stress all devices with enhanced test capability multisite testing at the wafer level for efficient throughput tests at high temperature high temperature capability and materials chuck, prober, probe card with stiffener challenges. Within a wafer lot, occasionally an individual wafer will differ significantly from the yield of all the other wafers. These automated test solutions provide high volume, automated systemlevel testing and thermal testing, making it easy and affordable to conduct 100% slt. Nov 07, 2016 learn how the ats 5034 system level test platform tests integrated semiconductors at 5,000 uph to deliver improved yields and the lowest cost of test.
For more information on these and other solutions from kes, please fill out our contact form and we will respond as quickly as possible. The wlr paradigm offers several advantages over a sample burnin process monitor. Will showcase foxxptm solutions for wafer level burn in and test of logic, optical and memory. Best value professional windows hardware test tool on the market. The custom photodiode test system is a scalable system that provides a low cost, high performance, accelerated aging, burn in, and qualification testing for photodiodes specifically used in military, telecommunication, and aerospace applications. Wafer level reliability wafer level reliability testing. Waferlevel burnin will cut motorola costs ee times. While providing some much needed solutions, it also comes with its own set of challenges. Industry practices and trends overview and defnitions. Waferlevel test during burnin wltbi is an emerging practice in the semiconductor industry that allows testing to be performed simultaneously with burnin at the waferlevel. Rji technical sales your source for wafer level bi and test. A new waferlevel burnin wlbi technology is reported in this paper.
It effectively traps the loose debris which accumulates on the probe tip and shaft during waferlevel test. Learn how the ats 5034 systemlevel test platform tests integrated semiconductors at 5,000 uph to deliver improved yields and the lowest cost of test. Probe clean is a unique, highly crosslinked, nonconductive, and noncorrosive polymerbased probe cleaning material. We refer to this process as waferlevel testduringburnin. A fullyautomated, 48pin parametric test system is designed for wafer level testing of power semiconductor devices and structures up to 3kv. Sti3000 wafer probe test system solidus technologies, inc. At a high level this process involves stimulating the input ports with various test patterns also known as test vectors and comparing the output responses against expected results.
Wlbi driving factors cost reduction burn in was viewed as temporary well only bi until the new process is stable when it became stable, another new process. Wlbt waferlevel burnin and test helps to simplify the final manufacturing process and to reduce overall product cost. A fullyautomated, 48pin parametric test system is designed for waferlevel testing of power semiconductor devices and structures up to 3kv. Wafer level test and burn in wltbi refers to the process of subjecting semiconductor devices to electrical testing and burn in while they are still in wafer form.
Waferlevel burnin and test wlbt is a method for burningin devices while they are still unpackaged. For windows also available for linux stress test all the major subsystems of a computer for endurance, reliability and stability. Micro burnin techniques at waferlevel test to implement. Test scheduling for waferlevel testduringburnin of.
Systemlevel testing for semiconductor devices youtube. Testpattern ordering for waferlevel testduringburnin. Wafer level burn in and test wlbt is a method for burning in devices while they are still unpackaged. Wafer level burnin and test how is wafer level burnin. Wlr testing is a statistical process control tool that gathers data through. Test during burnin at the waferlevel enhances the bene. The physical constraints introduced by multisite wafer level chip scale testing has presented challenges to traditional techniques used for. Dvi worked with a major semiconductor manufacturer developing a unique wafer level burn in system technology. Us6788094b2 us10326,423 us32642302a us6788094b2 us 6788094 b2 us6788094 b2 us 6788094b2 us 32642302 a us32642302 a us 32642302a us 6788094 b2 us6788094 b2 us 6788094b2 authority. As the industry moves towards kgd and multichip modules there is an increasing need for burnin systems capable of performing the burnin test function at the wafer level.
Distributed test wafer probe, in situ test between key assembly steps and final test slt and ate for 2. Microchips tripletest flow is currently the most robust testing procedure for. Wafer level stress data successfully used as early burn in predictor. Waferlevel parametric tester targets power sic, gan. Wafer level stress data successfully used as early burnin. Abstract waferlevel test during burnin wltbi is a promising technique to reduce test and burnin costs in semi conductor manufacturing. Microchips tripletest flow is currently the most robust testing procedure for serial eeprom. Waferlevel burnin with test solid state technology. Wafer level reliability test solutions greater reliability testing confidence from lab to fab wafer level reliability test solutions keithley instruments has long been an industry leader in both overall parametric test technology and wafer level reliability wlr testing. Last but not least, a main challenge is the correlation between the wafer level test and final test. For example, the test structure designer has to follow design rules of the fab for the wafer under test. The custom photodiode test system is a scalable system that provides a low cost, high performance, accelerated aging, burnin, and qualification testing for photodiodes specifically used in military, telecommunication, and aerospace applications. Aehr test systems to introduce next generation foxxp.
These wafer level burnin systems are being designed around several driving factors. Moving burnin to the wafer level allows for simplification of package test by eliminating both package burnin and post burnin test, requiring just a single package test insertion with the possible addition of systemlevel tests. As the industry moves towards kgd and multichip modules there is an increasing need for burn in systems capable of performing the burn in test function at the wafer level. The advantage of wafer level testing is that these semiconductor devices can. The monitoring of device responses while applying suitable test stimuli during wlbi leads to the easier identi. Form today announced the introduction of the latest addition to its harmonytm family of fullarea, 300mm wafer probe solutionsthe harmony waferlevel burnin wlbi probe card. Testpattern ordering for waferlevel testduringburnin sudarshan bahukudumbi and krishnendu chakrabarty department of electrical and computer engineering duke university, durham, nc 27708 abstractwaferlevel test during burnin wltbi is a promising technique to reduce test and burnin costs in semiconductor manufacturing. Not only does wafer level burnin and test offer an opportunity to experience significant cost and throughput benefits, but it is required as an enabling technology if we are going to be successful in offering module and systeminpackage solutions to our customers, said kelly folts, product engineering and program manager with motorola. Burn in is a temperaturebias reliability stress test used in detecting and screening out potential early life failures. Automation of generation of entire test programs for ate. By this, firm contacts on 2,756 bond pads provided on a 6 diameter wafer are made in a temperature range from room to 125c. Aehr test systems is a worldwide provider of test systems for burn in test equipment and logic, optical and memory integrated circuits worldwide.
Production test of the asic is a key component of what we do and is an important element in the process of providing high quality product that is reliable and free of defects. Techniques for performing wafer level burn in and test of semiconductor devices include a test substrate having active electronic components such as asics mounted to an interconnection substrate or incorporated therein, metallic spring contact elements effecting interconnections between the asics and a plurality of devicesunder test duts on a wafer under test wut, all disposed in a vacuum. Waferlevel test and burnin wlb waferlevel test and burnin wltbi refers to the process of subjecting semiconductor devices to electrical testing and burnin while they are still in wafer form. Gelsinger said, were already burning in devices in expensive chambers, and by using dft techniques, we can actually bring a great deal of the testing into the burnin process. Optimized for use with the latest compound power semiconductor materials including silicon carbide sic and gallium nitride gan, the fully integrated keithley s540 power semiconductor test system is said to perform all highvoltage, lowvoltage, and. Kes technologies provide solutions for test, burnin, systemlevel test, wafer level burnin and much more. The most obvious and immediate advantage of wlr testing is its ability to supply realtime information. This type of testing applies a high level of stress to special test structures on the wafer and measures the degradation caused by this stress. Waferlevel testing refers to a critical process of subjecting integrated circuits and semiconductor devices to electrical testing while they are still in wafer form. The harmony wlbi probe card is designed to maximize throughput. Kes technologies provide solutions for test, burn in, system level test, wafer level burn in and much more. Wlr testing is a statistical process control tool that gathers data through parametric testing to identify process anomalies that could degrade longterm device reliability.
Wafer level burnin and test how is wafer level burnin and. Distributed test wafer probe, insitu test between key assembly steps and final test slt and ate for 2. It is so important and critical to the quality of what we produce that we conduct all wafer probe and ate inhouse at our swindon facility. Wafer level stress data successfully used as early burnin predictor. Wafer level burn in and test how is wafer level burn in and test abbreviated. Test during burnin is a hot topic evaluation engineering. Tutorial on motorola wafer level burn in and test 2002 southwest test workshop. Move it closer to the source of the problem do it cheaper maybe full wafer bi and test. Test scheduling for waferlevel testduringburnin of core. Edn motorola claims first wafer level burnin and test. Burn in is a temperaturebias reliability stress test used in detecting and screening out potential early life device failures. Aimed at solving the low efficiency of the traditional test system and simplifying its laborious operation, we carefully compared different mmwave instruments of many companies 36,37,38,39, then put forward a new allinone waferlevel solution for mmic automatic testing. Wafer level burnin and test how is wafer level burnin and test abbreviated.
Dvi worked with a major semiconductor manufacturer developing a unique wafer level burnin system technology. Aehr test fox bi system partial darpa funding nhk spring, yokohama, japan, micropogos electroglas for wafer alignment wafer alignment to the bi pwb is done offline and waferpwb cassettes are held together with air pressure fox equipment provides stimulus and test electronics, thermal management, dut power. Allinone waferlevel solution for mmic automatic testing. The third level of testing is used to identify manufacturing defects or faults. Oct 08, 2010 electroglas provides advanced wafer probers, device handlers, test floor management software and services with modern tools for semiconductor industry.
Waferlevel testing and test during burnin for integrated. Mpi integration of celadon systems high performance probe cards inside mpi automated probe systems like ts2000se or ts3000se, makes the high density, multisite, high temperature wafer level reliability testing easy and versatile. Our systems are capable of testing and burningin thousands of photonic devices on wafers in parallel for minutes to. The four papers in this session look at waferlevel test from a number of different perspectives. Aehr test systems to participate in two upcoming investor. The solution adopts the dualcore hardware topology and a threelevel.
Waferlevel test and burnin refers to the process of subjecting semiconductor devices to electrical testing and burnin while they are still in. These wafer level burn in systems are being designed around several driving factors. Department of electrical and computer engineering duke university, durham, nc 27708. Consumers are demanding higher capability portable electronic devices ranging from cellular telephones with built in cameras to pdas that are. Aehr test systems is a worldwide provider of test systems for burnin test equipment and logic, optical and. June 9, 2002 page 3 direct contact key milestonesqualified process for c4fccbga for powerpc june 2001 product using goremate demonstrated test capability for ncsg dsp march 2002 product and tspg 32bit mcu. Pdf wafer level stress data successfully used as early burn. This in turn drives the need for full functional test at probe since traditional package and final test is eliminated from the manufacturing process. Only with a good correlation can a comparison of the achieved results be undertaken thus giving the test engineer confidence in his early testing.
Consequently, bist and waferlevel burnin are aimed primarily at reducing the test cost for logic devices. At the core of the test system is stis proprietary drive sense technology dst. Burnin is a temperaturebias reliability stress test used in detecting and screening out potential early life device failures. Waferlevel parametric tester targets power sic, gan devices. Waferlevel test and burnin wltbi refers to the process of subjecting semiconductor devices to electrical testing and burnin while they are still in wafer form. True, full, tester per pin capabilities to ensure your devices are functioning correctly and not just powered on. Wafer level burnin system delta v instruments, inc. However, the testing of multiple cores of a soc in parallel during wltbi leads to constantlyvarying device power during the duration of the test. Techniques for performing waferlevel burnin and test of semiconductor devices include a test substrate having active electronic components such as asics mounted to an interconnection substrate or incorporated therein, metallic spring contact elements effecting interconnections between the asics and a plurality of devicesundertest duts on a waferundertest wut, all disposed in a vacuum. Wafer level burnin wlbi and test parallel, dynamic, excitation of all devices on a wafer to screen for marginal devices for infant mortality by dynamically stressing the integrated circuit at elevated temperature and voltage. Session 6 and, at the wafer level for many in the industry, performing final test at the wafer level is still a novel idea. The proposed techniques are expected to bridge the gap between wafer sort and package test, by providing coste.
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